1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and more particularly to a method for manufacturing a vertical type MOS field effect transistor.
2. Description of Related Art
FIG. 1 is a cross sectional view showing the structure of a P channel vertical type field effect transistor. In the P channel vertical type field effect transistor shown in FIG. 1, there is used a P.sup.+ -type semiconductor substrate having a P-type semiconductor layer 2 formed thereon. On the surface of the P-type semiconductor layer 2 are formed N-type base regions 3 in each of which a P.sup.+ -type source region 4 is formed. A gate oxide film 5 is provided over the surfaces of a part of the P.sup.+ -type source region 4, the N-type base region 3, the P-type semiconductor layer 2, the N-type base region 3 and a part of the P.sup.+ -type source region 4. A polysilicon layer 6 is formed on the gate oxide film 5. The polysilicon layer 6 is covered with an insulating film 7 made of PSG (phosphor-silicate glass) on which metal such as aluminium is deposited to form a source electrode 8. Metal such as nickel is deposited on the back surface of the substrate 1 to form a drain electrode 9.
Generally, a few tens to a few hundred thousands of such a unit (cell) are arranged on a chip to form a device.
FIGS. 2A to 2E show a conventional manufacturing method of the P channel vertical type field effect transistor shown in FIG. 1.
First, as shown in FIG. 2A, the P-type epitaxial growth semiconductor layer 2 having a resistivity of 0.4 to 4.0 .OMEGA.cm and a thickness of 5 to 30 .mu.m is formed on the P.sup.+ -type semiconductor substrate having a resistivity of about 0.01 .OMEGA.cm. Then, after a well region and a field oxide film region are formed, the gate oxide film 5 of 300 to 1000 .ANG. in thick is formed on the surface of the P-type semiconductor layer 2. Next, as shown in FIG. 2B, a non-doped polysilicon layer 6 of 5000 to 10000 .ANG. in thick is grown on the gate oxide film 5.
Next, as shown in FIG. 2C, the polysilicon layer 6 is etched by use of photolithography technology to form a gate electrode on which an oxide film 13 is grown for preventing a channeling phenomenon in ion injection. Then, phosphorus ions are injected in the semiconductor layer 2 with a dose amount of 1.times.10.sup.12 to 8.times.10.sup.13 cm.sup.-2 and the acceleration voltage of 120 KeV in self-alignment with the etched polysilicon layer 6 as a mask. Subsequently, heat treatment is performed at 1140.degree. C. for 100 to 400 minutes so that the N-type base region 3 is formed.
Next, as shown in FIG. 2D, another ion injection process for injecting P.sup.+ ions is performed for back gate sections 11 of the N-type base region 3 after a resist 14 which has openings at the back gate sections 11. Thus, a contact characteristic with the source electrodes 4 which are formed in the following processes is improved. At this time, the P.sup.+ ions are not injected in the polysilicon layer 6.
Subsequently, as shown in FIG. 2E, the photolithography technology is applied to the back gate section 11 such that it is covered with a resist 15. Then, boron ions are injected with a dose amount of 5.times.10.sup.15 to 1.times.10.sup.16 cm.sup.-2 and the acceleration voltage of 50 KeV. After the resist 15 is removed, heat treatment is performed at a temperature of 850.degree. to 900.degree. C. for 10 to 60 minutes. At this time, the P.sup.+ -type source regions 4 are not only formed but also the polysilicon layer 6 is of P.sup.+ -type.
Next, as shown in FIG. 1, the PSG are deposited by a CVD method to form a PSG layer of 5000 to 10000 .ANG.. An opening is formed in a part of the PSG layer by use of photolithography technology for forming a contact section and aluminium is deposited in the opening to form the source electrode 8. Thereafter, a metal such as nickel is deposited on the back surface of the substrate 1 to form the drain electrode 9.
For manufacturing the above semiconductor device, in the Japanese Unexamined Patent Publication Tokukaihei 1-260856, after a polysilicon layer 6 has been grown, the boron ion injection and subsequently the phosphorus ion injection are performed and then heat treatment is performed, as shown in FIG. 3A. In this example, boron ions diffuse toward the gate insulating film more than phosphorus ions do, so that the getter effect based on the phosphorus ions cannot be achieved sufficiently.
In addition, in the Japanese Unexamined Patent Publication Tokukaihei 2-291174, after the field oxide film is formed, phosphorus ion injection is performed and then boron ions are injected after patterning to make the polysilicon layer 6 to be of P-type, as shown in FIG. 3B. However, any heat treatment is not performed at all.
In the conventional methods mentioned above, the heat treatment after the boron ion injection causes the boron ions to diffuse from the polysilicon layer 6 toward the gate insulating film 5 and further to pass through the gate insulating layer 5. Therefore, there result in the low initial gate threshold voltage or the dispersion thereof, or low reliability which is considered to be directed because of generation of interface levels between the gate insulating film and the surface of the semiconductor device. Because the heat treatment is not performed after the phosphorus ion injection in the above Tokukaihei 2-29117, the phosphorus ions cannot be diffused sufficiently so that there is a lack of the capability of capturing movable ions such as Na ions and K ions in the vicinity of the gate insulating film, resulting in the problem of reliability and the problem on mass production.